1. Field of the Invention
The present invention relates to a successive approximation register (SAR) analog to digital converter (ADC). In particular, the present invention relates to a SAR ADC and a method of performing successive approximation for analog to digital conversion based on a capacitor array.
2. Discussion of the Related Art
SAR ADC converters generally comprise one or more n-bit converters that operate in parallel. Each n-bit converter is arranged to sample an input voltage, and generates an n-bit digital value corresponding to the amplitude of the input voltage.
Generating the n-bit digital value generally involves sampling the input signal by a set of capacitors having binary weighted capacitance values corresponding to the most significant to least significant bits of the n-bit output signal. The capacitors are coupled to an input of a comparator, and a reference voltage is supplied to the other input of the comparator. A trial and error process is then used to determine what combination of high and low voltages coupled to each capacitor in turn balances the comparator.
In certain applications, such as mobile device applications, it is desirable to minimize the surface area of SAR ADCs, without compromising the accuracy of the device. There is thus a need for an improved SAR ADC having high accuracy and a reduced surface area and complexity.